The 9500 series Xilinx CPLD is memory mapped into external address space using the atXmega's external bus interface. The CPLD provides a linear address mapping of all 14 Servo Channel Captures. Alternatively, the CPLD will detect frame ends and signal an interrupt to transfer all 14 Captures via DMA to an assigned data memory location within the atxmega. 14 PWM outputs will be sent to the CPLD from the atxmega. Failsafe routing of servo input to servo output, or autopilot takeover etc will be handled by the CPLD as well. This approach to input capture was selected to avoid using any of the 8-Channel event system resources within the atxmega or possibly only 1 event for DMA. Input capture is jitter free, high resolution and provides negligible cpu loading.