Autonomous Robotic Hardware Development

XmegaPilot CPLD Provides Failsafe Functionality

The 9500 series Xilinx CPLD is memory mapped into external address space using the atXmega's external bus interface. The CPLD provides a linear address mapping of all 14 Servo Channel Captures. Alternatively, the CPLD will detect frame ends and signal an interrupt to transfer all 14 Captures via DMA to an assigned data memory location within the atxmega. 14 PWM outputs will be sent to the CPLD from the atxmega. Failsafe routing of servo input to servo output, or autopilot takeover etc will be handled by the CPLD as well. This approach to input capture was selected to avoid using any of the 8-Channel event system resources within the atxmega or possibly only 1 event for DMA. Input capture is jitter free, high resolution and provides negligible cpu loading.

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Comment by Michael Zaffuto on June 11, 2010 at 1:28am
Thanks Lew...I fixed the underlining settings!
Comment by Lew Payne on June 10, 2010 at 2:08am
None of the links, included in the above message, are highlighted or underlined. Oh, I see... the text is a bit more bold, but almost imperceptibly so. How annoying... considering that underline is the standard for denoting a link as clickable.
Comment by Lew Payne on June 10, 2010 at 2:02am
If I don't get lazy over the weekend, I'll snap some pics of my two development boards. I had a really difficult time finding an STM32 based dev board that I liked... I'm quite picky, and wanted a certain feature set on-board as well as a small breadboard. I would have settled for MikroElektronica boards if they made one for STM32 and the TI, but they didn't (their ARM board is LPC2148 based). They do have a PSoC board, but I won't buy one until I have a good feel for how advantageous the platform would be for me.

Here's my STM32 development board and my TI development board, by the way (hah... no need to take pics after all).

About the EKF... I would strongly consider using an unscented Kalman filter, of the sigma-delta square root variety. I'm also going to try and model GPS latency compensation into it, but that will be much harder (the research is there... I just need to work out an implementation) - see this discussion for details.

As for the TI processor, I'm fortunate to know an engineer in a company that develops with it, with a large support group available to handle tough situations. I just got the board a month ago, as a result of him agreeing to help me learn the in's and out's of it, as we co-develop some flight software/hardware together. It was a good opportunity for me to learn a new and powerful processor (DSP, at that) in a real-life situation.
Comment by Michael Zaffuto on June 9, 2010 at 10:14pm
Good choices on processors Lew...the TMS320F28835 is the processor I had in mind to work with XmegaPilot as a coprocessor. The variant is called DelfinoPilot..I setup a private ning network for it a while back but put it on the backburner for now to concentrate on XmegaPilot. DeflinoPilot uses the entire XmegaPilot as currently defined as a front end leaving the '28835 maximum time to crunch through matrices as fast as possible. The multiple processor approach is also to keep the EKF within the 32K program limitiation imposed by the free limited-unlimited-time code composer studio software. The rest of the 'mundane' chores would be handled by the atXmega. There are some chips I'm eagerly awaiting that may change my mind about the '28335, it seems like the best choice at the moment. BTW...the PSOC5's do look pretty cool.

Also, how is it going regarding your experiences with the TI chip...easy to program...gotchas...etc?
Comment by Lew Payne on June 9, 2010 at 4:47pm
Anyone use the Cypress PSoC (Programmable System on Chip)? I'm curious about it, but don't want to invest the time into learning enough about it to make an informed decision. My current development systems are STM32 (CORTEX-M3) based, as well as TI TMS320F28335 (with floating point).
Comment by Michael Zaffuto on June 7, 2010 at 9:53pm

This block diagram shows the I/O capability of the 9500. 5V full swing PWM pulses are tolerated directly into this CPLD. Series resistors will be used for a little safety though. The output is limited to 3.3V CMOS levels. I will be including a 3.3Volt to 5Volt translator/buffer to obtain 0 to 5volt output swing for good noise margins and drive levels. Cost of CPLD/Buffer Pair for Servo Input Capture/Manual-Auto Multiplexer/Failsafe appears to be cheaper and potententially more capable than other alternatives that have been explored.

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