Spartan FPGAs versus CPLDs

[Michael Zaffuto]

FPGA Just Might WIN!
Working hard on implementing the Input Capture-Multiplexer.
I'm working with Xilinx Webpack 12.1 and I have a little help with Atium Designer as well :)

It's starting to look like the CPLD won't have the resources I need in a sized package or price I'm looking for.
There are some good options in the Spartan family in the $6 to $12 range that I'm exploring.
I have 3 Xilinx development platform's I'm testing with, a regular Spartan-3, a Spartan-3E and a CoolRunner2 with 9500xl.

The Input Capture per channel is 12 bits with 14 channels of capture. This requires 168 Flip Flops for counters. The design is also set up to transfer the IC values as they become available into an addressable memory block 12bits wide x 14 deep, needing another 168 Flip Flops. Internal Address latching needs a nibble of flip flops as well.
There is some additonal logic, maybe lots more, that will be running as well...will provide additional details as I verify going forward.

The end goal will be an open source FPGA project that can be compiled and sythesized using just the freely downloadable Xilinx Webpack and burned into the programmable device using a simple cable.

[Michael Zaffuto]

Wow, how cool, Altium corporation sent me a tweet!